pub(super) fn choose_opcode_selector(pass: Pass, sub_cycle: SubCycle) -> OpcodeSelector {

        let n = sub_cycle.as_usize() % 36;

        if n == 1 {

            OpcodeSelector::Target

        } else if n == 19 {

            OpcodeSelector::Branch

        } else if n == 12 || n == 24 {

            OpcodeSelector::WideMul

        } else if (n % 3) == 0 {

            OpcodeSelector::Mul

            match pass {

                Pass::Original => OpcodeSelector::Normal,

                Pass::Retry => OpcodeSelector::ImmediateSrc,

    }

    pub(crate) fn new(rng: &'r mut R) -> Self {

        Generator {

            rng: RngBuffer::new(rng),

            scheduler: Scheduler::new(),

            validator: Validator::new(),

            last_selector_result_op: None,

        }

    }

    fn select_register(&mut self, reg_options: &RegisterSet) -> Result<RegisterId, ()> {

        match reg_options.len() {

            0 => Err(()),

            1 => Ok(reg_options.index(0)),

            num_options => {

                let num_options: u32 = num_options

                    .try_into()

                    .expect("register set length always fits in u32");

                let index = self.rng.next_u32() % num_options;

                Ok(reg_options.index(

                    index

                        .try_into()

                        .expect("register set length always fits in usize"),

                ))

    }

    fn select_op<'a, T, const SIZE: usize>(&mut self, options: &'a [T; SIZE]) -> &'a T {

        &options[(self.rng.next_u8() as usize) % options.len()]

    }

    fn select_constant_weight_bit_mask(&mut self, num_ones: usize) -> u32 {

        let mut result = 0_u32;

        let mut count = 0;

        while count < num_ones {

            let bit = 1 << ((self.rng.next_u8() as usize) % 32);

            if (result & bit) == 0 {

                result |= bit;

                count += 1;

            }

        result

    }

    fn select_nonzero_u32(&mut self, mask: u32) -> u32 {

            let result = self.rng.next_u32() & mask;

            if result != 0 {

                return result;

            }

    }

    pub(crate) fn generate_program(&mut self, output: &mut InstructionVec) -> Result<(), Error> {

        assert!(output.is_empty());

        while !output.is_full() {

            match self.generate_instruction() {

                Ok((inst, regw)) => {

                    let state_advance = self.commit_instruction_state(&inst, regw);

                    output.push(inst);

                    if let Err(()) = state_advance {

                        break;

                    }

        self.validator

            .check_whole_program(&self.scheduler, output)

            .map_err(|()| Error::ProgramConstraints)

    }

    fn generate_instruction(&mut self) -> Result<(Instruction, RegisterWriter), ()> {

            if let Ok(result) = self.instruction_gen_attempt(Pass::Original) {

                return Ok(result);

            }

            if let Ok(result) = self.instruction_gen_attempt(Pass::Retry) {

                return Ok(result);

            }

            self.scheduler.stall()?;

    }

    fn choose_opcode(&mut self, pass: Pass) -> Opcode {

        let op = loop {

            let sub_cycle = self.scheduler.instruction_stream_sub_cycle();

            let op = model::choose_opcode_selector(pass, sub_cycle).apply(self);

            if let Ok(()) = constraints::opcode_pair_allowed(self.last_selector_result_op, op) {

                break op;

            }

        self.last_selector_result_op = Some(op);

        op

    }

    fn instruction_gen_attempt(&mut self, pass: Pass) -> Result<(Instruction, RegisterWriter), ()> {

        let op = self.choose_opcode(pass);

        let plan = self.scheduler.instruction_plan(op)?;

        let (inst, regw) = self.choose_instruction_with_opcode_plan(op, pass, &plan)?;

        debug_assert_eq!(inst.opcode(), op);

        self.scheduler.commit_instruction_plan(&plan, &inst);

        Ok((inst, regw))

    }

    fn choose_src_reg(

        &mut self,

        op: Opcode,

        timing_plan: &InstructionPlan,

    ) -> Result<RegisterId, ()> {

        let src_set = RegisterSet::from_filter(|src| {

            self.scheduler

                .register_available(src, timing_plan.cycle_issued())

        });

        let src_set = constraints::src_registers_allowed(src_set, op);

        self.select_register(&src_set)

    }

    fn choose_src_dst_regs(

        &mut self,

        op: Opcode,

        pass: Pass,

        writer_info_fn: fn(RegisterId) -> RegisterWriter,

        timing_plan: &InstructionPlan,

    ) -> Result<(RegisterId, RegisterId, RegisterWriter), ()> {

        let src = self.choose_src_reg(op, timing_plan)?;

        let writer_info = writer_info_fn(src);

        let dst = self.choose_dst_reg(op, pass, writer_info, Some(src), timing_plan)?;

        Ok((src, dst, writer_info))

    }

    fn choose_src_dst_regs_with_writer_info(

        &mut self,

        op: Opcode,

        pass: Pass,

        writer_info: RegisterWriter,

        timing_plan: &InstructionPlan,

    ) -> Result<(RegisterId, RegisterId), ()> {

        let src = self.choose_src_reg(op, timing_plan)?;

        let dst = self.choose_dst_reg(op, pass, writer_info, Some(src), timing_plan)?;

        Ok((src, dst))

    }

    fn choose_dst_reg(

        &mut self,

        op: Opcode,

        pass: Pass,

        writer_info: RegisterWriter,

        src: Option<RegisterId>,

        timing_plan: &InstructionPlan,

    ) -> Result<RegisterId, ()> {

        let validator = self

            .validator

            .dst_registers_allowed(op, pass, writer_info, src);

        let dst_set = RegisterSet::from_filter(|dst| {

            self.scheduler

                .register_available(dst, timing_plan.cycle_issued())

                && validator.check(dst)

        });

        self.select_register(&dst_set)

    }

    fn choose_instruction_with_opcode_plan(

        &mut self,

        op: Opcode,

        pass: Pass,

        plan: &InstructionPlan,

    ) -> Result<(Instruction, RegisterWriter), ()> {

        Ok(match op {

            Opcode::Target => (Instruction::Target, RegisterWriter::None),

            Opcode::Branch => (

                Instruction::Branch {

                    mask: self.select_constant_weight_bit_mask(model::BRANCH_MASK_BIT_WEIGHT),

                },

                RegisterWriter::None,

            ),

                let regw = RegisterWriter::UMulH(self.rng.next_u32());

                let (src, dst) = self.choose_src_dst_regs_with_writer_info(op, pass, regw, plan)?;

                (Instruction::UMulH { src, dst }, regw)

                let regw = RegisterWriter::SMulH(self.rng.next_u32());

                let (src, dst) = self.choose_src_dst_regs_with_writer_info(op, pass, regw, plan)?;

                (Instruction::SMulH { src, dst }, regw)

                let regw = RegisterWriter::Mul;

                let (src, dst, regw) = self.choose_src_dst_regs(op, pass, regw, plan)?;

                (Instruction::Mul { src, dst }, regw)

                let regw = RegisterWriter::AddSub;

                let (src, dst, regw) = self.choose_src_dst_regs(op, pass, regw, plan)?;

                (Instruction::Sub { src, dst }, regw)

                let regw = RegisterWriter::Xor;

                let (src, dst, regw) = self.choose_src_dst_regs(op, pass, regw, plan)?;

                (Instruction::Xor { src, dst }, regw)

                let regw = RegisterWriter::AddSub;

                let left_shift = (self.rng.next_u32() & 3) as u8;

                let (src, dst, regw) = self.choose_src_dst_regs(op, pass, regw, plan)?;

                (

                    Instruction::AddShift {

                        src,

                        dst,

                        left_shift,

                    },

                    regw,

                )

                let regw = RegisterWriter::AddConst;

                let src = self.select_nonzero_u32(u32::MAX) as i32;

                let dst = self.choose_dst_reg(op, pass, regw, None, plan)?;

                (Instruction::AddConst { src, dst }, regw)

                let regw = RegisterWriter::XorConst;

                let src = self.select_nonzero_u32(u32::MAX) as i32;

                let dst = self.choose_dst_reg(op, pass, regw, None, plan)?;

                (Instruction::XorConst { src, dst }, regw)

                let regw = RegisterWriter::Rotate;

                let right_rotate: u8 = self.select_nonzero_u32(63) as u8;

                let dst = self.choose_dst_reg(op, pass, regw, None, plan)?;

                (Instruction::Rotate { dst, right_rotate }, regw)

    }

    fn commit_instruction_state(

        &mut self,

        inst: &Instruction,

        regw: RegisterWriter,

    ) -> Result<(), ()> {

        self.validator.commit_instruction(inst, regw);

        self.scheduler.advance_instruction_stream(inst.opcode())

    }

    fn apply<R: RngCore>(&self, gen: &mut Generator<'_, R>) -> Opcode {

        match self {

            OpcodeSelector::Target => Opcode::Target,

            OpcodeSelector::Branch => Opcode::Branch,

            OpcodeSelector::Mul => Opcode::Mul,

            OpcodeSelector::Normal => *gen.select_op(&model::NORMAL_OPS_TABLE),

            OpcodeSelector::ImmediateSrc => *gen.select_op(&model::IMMEDIATE_SRC_OPS_TABLE),

            OpcodeSelector::WideMul => *gen.select_op(&model::WIDE_MUL_OPS_TABLE),

    }