Enum Instruction

pub(crate) enum Instruction {
    Mul {
        dst: RegisterId,
        src: RegisterId,
    },
    UMulH {
        dst: RegisterId,
        src: RegisterId,
    },
    SMulH {
        dst: RegisterId,
        src: RegisterId,
    },
    AddShift {
        dst: RegisterId,
        src: RegisterId,
        left_shift: u8,
    },
    AddConst {
        dst: RegisterId,
        src: i32,
    },
    Sub {
        dst: RegisterId,
        src: RegisterId,
    },
    Xor {
        dst: RegisterId,
        src: RegisterId,
    },
    XorConst {
        dst: RegisterId,
        src: i32,
    },
    Rotate {
        dst: RegisterId,
        right_rotate: u8,
    },
    Target,
    Branch {
        mask: u32,
    },
}

Define the HashX virtual instruction set

Variants

Mul

64-bit multiply of two registers, discarding overflow.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

UMulH

Unsigned 64x64 to 128-bit multiply, saving only the upper half.

Result is written to dst, and the low 32 bits are saved for the next Branch test.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

SMulH

Signed 64x64 to 128-bit multiply, saving only the upper half.

Result is written to dst, and the low 32 bits are saved for the next Branch test.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

AddShift

Shift source register left by a constant amount, add, discard overflow.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

left_shift: u8

Number of bits to left shift by (0..=3 only)

AddConst

64-bit addition by a sign-extended 32-bit constant.

Fields

dst: RegisterId

Destination register

src: i32

Source immediate, sign-extended from 32-bit to 64-bit

Sub

64-bit subtraction (dst - src), discarding overflow.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

Xor

64-bit XOR of two registers.

Fields

dst: RegisterId

Destination register

src: RegisterId

Source register

XorConst

XOR a 64-bit register with a sign-extended 32-bit constant.

Fields

dst: RegisterId

Destination register

src: i32

Source immediate, sign-extended from 32-bit to 64-bit

Rotate

Rotate a 64-bit register right by a constant amount.

Fields

dst: RegisterId

Destination register

right_rotate: u8

Number of bits to rotate right by (0..=63 only)

Target

Become the target for the next taken branch, if any.

Branch

One-shot conditional branch to the last Target.

Fields

mask: u32

32-bit branch condition mask

This is tested against the last UMulH/SMulH result. (The low 32 bits of the instruction result, which itself is the upper 64 bits of the multiplication result.)

If (result & mask) is zero and no branches have been previously taken, we jump back to the Target and remember not to take any future branches. A well formed program will always have a Target prior to any Branch.

Implementations

impl Instruction

pub(crate) fn opcode(&self) -> Opcode

Get this instruction’s Opcode.

pub(crate) fn destination(&self) -> Option<RegisterId>

Get this instruction’s destination register, if any.

Trait Implementations

impl Clone for Instruction

fn clone(&self) -> Instruction

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Instruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Instruction

fn eq(&self, other: &Instruction) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for Instruction

impl StructuralPartialEq for Instruction