Expand description
Scheduling model for program generation
HashX uses a simple scheduling model inspired by the Intel Ivy Bridge microarchitecture to choose registers that should be available and avoid stalls.
Modules§
- model 🔒
- Scheduling information for each opcode
Structs§
- Cycle 🔒
- Cycle timestamp
- Data
Schedule 🔒 - Latency tracking for all relevant CPU registers
- Exec
Port 🔒Index - One single execution port
- Exec
Schedule 🔒 - Execution schedule for all ports
- Instruction
Plan 🔒 - Detailed execution schedule for one instruction
- Micro
OpPlan 🔒 - Detailed execution schedule for one micro-operation
- Port
Schedule 🔒 - Busy tracking for one CPU execution port
- Scheduler 🔒
- Overall state for the simulated execution schedule
- Simple
BitArray 🔒 - Simple packed bit array implementation
- SubCycle 🔒
- Sub-cycle timestamp