Struct Scheduler

pub(crate) struct Scheduler {
    sub_cycle: SubCycle,
    cycle: Cycle,
    exec: ExecSchedule,
    data: DataSchedule,
}

Overall state for the simulated execution schedule

Fields

sub_cycle: SubCycle

Current timestamp in the schedule, in sub-cycles

Sub-cycles advance as code is generated, modeling the time taken to fetch and decode instructions.

cycle: Cycle

Current timestamp in the schedule, in cycles

Derived from sub_cycle.

exec: ExecSchedule

State for scheduling execution by fitting micro-ops into execution ports

data: DataSchedule

State for scheduling register access by keeping track of data latency

Implementations

impl Scheduler

pub(crate) fn new() -> Self

Create a new empty execution schedule at cycle 0

pub(crate) fn stall(&mut self) -> Result<(), ()>

Stall for one cycle.

Used when register allocation fails. Returns Ok if we had enough time, or Err if we ran out.

pub(crate) fn instruction_stream_sub_cycle(&self) -> SubCycle

Return the current instruction fetch/decode timestamp in sub-cycles.

fn advance(&mut self, n: usize) -> Result<(), ()>

Advance forward in time by some number of sub-cycles.

Stops just before reaching Cycle::target(), where we stop scheduling new instructions.

pub(crate) fn advance_instruction_stream( &mut self, op: Opcode, ) -> Result<(), ()>

Advance time forward by the modeled duration of the instruction fetch and decode, in sub-cycles.

Returns Ok if we still have enough time to schedule more, or Err if the schedule would be full.

pub(crate) fn instruction_plan(&self, op: Opcode) -> Result<InstructionPlan, ()>

Calculate a timing plan describing the cycle and execution units on which a particular opcode could run, at the earliest.

pub(crate) fn commit_instruction_plan( &mut self, plan: &InstructionPlan, inst: &Instruction, )

Commit to using a plan returned by Self::instruction_plan(), for a particular concrete Instruction instance.

Marks as busy each execution unit cycle in the plan, and updates the latency for the Instruction’s destination register if it has one.

pub(crate) fn register_available(&self, reg: RegisterId, cycle: Cycle) -> bool

Look up if a register will be available at or before the indicated cycle.

pub(crate) fn overall_latency(&self) -> Cycle

Return the overall data latency.

This is the Cycle at which we expect every register to reach its final simulated state.

Trait Implementations

impl Clone for Scheduler

fn clone(&self) -> Scheduler

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Scheduler

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Scheduler

fn default() -> Scheduler

Returns the “default value” for a type.